The present disclosure relates to a digital PLL circuit that generates an oscillation clock having a desired oscillating frequency.
Digitized PLL circuits are conventionally known (see Japanese Patent Publication No. 2002-76886 (Patent Document 1), for example). A digital PLL circuit disclosed in Patent Document 1 adds up frequency control words in synchronization with a reference clock to obtain a cumulative value, and also increments a phase value in synchronization with an output clock. This digital PLL circuit calculates the difference between the cumulative value and the phase value as a phase error value, and controls the frequency of the output clock in accordance with the phase error value. In this way, the frequency of the output clock is controlled so that the magnification of the frequency of the output clock with respect to the frequency of the reference clock is equal to the value indicated by the frequency control word. For example, for generation of an output clock of 225 MHz based on a reference clock of 100 MHz, the frequency control word is set at “2.25.”
Also, the digital PLL circuit of Patent Document 1 includes a time-to-digital converter for detection of a minute phase error (phase error smaller than one period of the output clock) between the reference clock and the output clock. The time-to-digital converter includes: a delay circuit made of a plurality of cascaded inverters; a plurality of registers configured to hold the outputs of the plurality of inverters in synchronization with a rising edge of the reference clock; and an edge detector configured to detect a time difference between a rising edge of the reference clock and a rising edge of the output clock based on the outputs of the plurality of registers. Having this time-to-digital converter, a minute phase error is detected with the delay time of each inverter as the minimum unit.